Personal computers commonly include a central processing unit (CPU) that executes instructions and stores data in main memory. The main memory is typically provided as one or more printed-circuit boards, each supporting integrated-circuit (IC) memory devices and coupled to the CPU via one or more main-memory buses. Specialized functions, such as graphics processing, can be passed to a separate card on a separate “expansion” bus. In a typical example, a CPU can assign resource-intensive graphics processes to a dedicated graphics card. Such systems improve overall performance, but are expensive and may not allocate communication resources efficiently. For example, relatively graphics-intensive processes may overwhelm the expansion bus, whereas less graphics-intensive processes may leave this resource underutilized.
U.S. Pat. No. 6,864,896 to Richard E. Perego details an improved computer architecture in which peripheral functionality is provided by “computing engines” located with the memory ICs on the main-memory modules. The computing engines can share main memory, which allows for more efficient memory allocation between the CPU and the peripheral engines, and communication bandwidth can be optimized over the common main-memory buses. These improvements can improve performance, save costs, or both.